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91400 rm (im) tw-1/22 ver.1.02g 31293 overview the LC86P6032 microcontroller, a new addition to the lc866000 series, is a 8-bit single chip cmos microcontroller with one-time prom. this microcontroller has the same function and pin assignment as for the lc866000 series mask rom version, and a 32k-byte prom. features (1) option switching using prom data the optional functions of the lc866000 series can be specified using prom data. the functions of the trial products can be evaluated using a mass production board. (2) internal one-time prom capacity : 32768 bytes (3) internal ram capacity : 512 bytes mask rom version prom capacity ram capacity lc866032 lc866028 lc866024 lc866020 lc866016 lc866012 lc866008 32512 bytes 28672 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes 8192 bytes 512 bytes 512 bytes 512 bytes 384 bytes 384 bytes 384 bytes 384 bytes (4) operating supply voltage : 4.5v to 6.0v (5) instruction cycle time : 0.98 s to 400 s (6) operating temperature range : -30 c to +70 c (7) pin and package compatible with the mask rom version (8) applicable mask rom version : lc866032/lc866028/lc866024/lc866020/lc866016/lc866012 /lc866008 (9) factory shipment : dip64s : qfp64e programming service we offer various services at nominal charges. these include rom writing, rom reading, and package stamping and screening. contact our local representatives for further information. 8-bit single chip microcontrolle r with one-time prom LC86P6032 ordering number : enn4212a cmos ic
LC86P6032 2/22 notice for use when using, please take note of the following. (1) differences between the LC86P6032 and the lc866000 series item LC86P6032 lc866032/28/24/20/16/12/08 port status at reset please refer to ?port status at reset? on the next page. operation after releasing reset the option is specified by degrees within 3ms after applying a ?h? level to the reset pin. the program located at 00h is executed. the program located at 00h is executed immediately after applying a ?h? level to the reset pin. output form of segment s0/t0 to s6/t6 s7/t7 to s15/t15 s16 to s23 s24 to s29 pulldown resistor not provided provided(fixed) provided(fixed) not provided pulldown resistor : provided/not provided specified by the option provided(fixed) specified by the option specified by the option operating supply voltage range (vdd) 4.5v to 6.0v 2.5v to 6.0v power dissipation refer to ?electrical characteristics? on the semiconductor news. LC86P6032 uses 256 bytes that is addressed on 7f00h to 7fffh in the program memory as the option configuration data area. this option configuration cannot execute all options which lc866000 series have. next tables show the options that correspond and not correspond to LC86P6032. LC86P6032 options option pins, circuits option settings configuration of input/output ports port 0 (can be specified for each bit.) 1. input : no pull-up mos transistor output : n-channel open drain 2. input : pull-up mos transistor output : cmos port 1 (can be specified for each bit.) 1. input : programmable pull-up mos transistor output : n-channel open drain 2. input : programmable pull-up mos transistor output : cmos port 7 pull-up mos transistor port 7 (can be specified for each bit.) 1. pull-up mos transistor not provided. 2. pull-up mos transistor provided. a kind of option not corresponding LC86P6032 option pins, circuits LC86P6032 lc866032/28/24/20/16/12/08 pull-down resistor of high voltage withstand output terminal s0/t0 to s6/t6 s16 to s23 s24 to s29 (specified in a bit) not provided provided(fixed) not provided specified by the option specified by the option specified by the option the port operation related to the option is different at reset. please refer to the next table.
LC86P6032 3/22 port configuration at reset pin option settings LC86P6032 lc866032/28/24/20/16/12/08 p0 input : no pull-up mos transistor output : n-channel open drain (same as for the mask version) input mode without pull-up mos transistor (output is off) input : pull-up mos transistor output : cmos input mode the pull-up mos transistor is not present during reset or several hundred microseconds after releasing reset. after that, the pull-up mos transistor is present. (output is off) input mode with pull-up mos transistor (output is off) p1 input : programmable pull-up mos transistor output : n-channel open drain (same as for the mask version) input mode without pull-up mos transistor (output is off) input : programmable pull-up mos transistor output : cmos (same as for the mask version) input mode without pull-up mos transistor (output is off) p7 pull-up mos transistor not provided (same as for the mask version) input mode without pull-up mos transistor pull-up mos transistor provided input mode the pull-up mos transistor is not present during reset or several hundred microseconds after releasing reset. after that, the pull-up mos transistor is present. input mode with pull-up mos transistor (2) option the option data is created by the option specified program ?su866000.exe?. the created option data is linked to the program area by the linkage loader ?l866000.exe?. (3) rom space LC86P6032 and lc866000 series use 256 bytes that is addressed on 07f00h to 07fffh in the program memory as the option specified data area. these program memory capacity are 32512 bytes that is addressed on 0000h to 7effh. (4) ordering information 1.when ordering identical mask rom and prom devices simultaneously. provide an eprom containing the target memory contents together with separate order forms for each of the mask rom and prom versions. 2. when ordering a prom device. provide an eprom containing the target memory contents together with an order form. 7fffh 7f00h 7effh 6fffh 5fffh 4fffh 3fffh 2fffh 1fffh 0000h 32k option data area 256 bytes lc866032 LC86P6032 28k option data area lc866028 24k option data area lc866024 20k option data area lc866020 16k option data area lc866016 12k option data area lc866012 8k option data area lc866008
LC86P6032 4/22 how to use (1) specification of option LC86P6032 is programmed after specifying option data. the option is specified by the su866000.exe. the specified option file and the file created by our macro assembler (m866000.exe) are linked by our linker (l866000.exe) which creates hex file, then the option code is put in the option specified area (07f00h to 07fffh) of its hex file. (2) how to program for the eprom the LC86P6032 can be programmed by an eprom programmer with attachments w86ep6032d and w86ep6032q. - recommended eprom programmer supplier eprom programmer advantest r4945, r4944, r4943 andou af-9704 aval pkw-1100, pkw-3000 minato electronics model 1890a - ?27512 (vpp=12.5v) intel high-speed programming? mode available. the address must be set to ?0000h to 07fffh? and the jumper (dasec) must be set ?off? at programming . (3) how to use the data security function ?data security? is a function to prevent eprom data from being read. instructions on using the data security function : 1. set the jumper of attachment ?on?. 2. attempt to program the eprom. the eprom programmer will display an error. the error indication is a result of normal activity of the data security feature. this is not a problem with the eprom programmer chip. (notes) the data security function is not carried out when the data of all addresses contain ?ff? at step 2 above. data security cannot be executed when the sequential operation ?blank=>program=>verify? is used at step 2 above. set the jumper ?off? after execution of data security. w86ep6032q w86ep6032d not data security not data security 1 pin mark of lsi data security data security 1 pin 1 pin
LC86P6032 5/22 pin assignment package dimension (unit : mm) 3071 sanyo : dip-64s(750mil) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/buz p17/pwm test1 res xt1 xt2 vss cf1 cf2 vdd p80/an0 p81/an1 p82/an2 p83/an3 p70/int0 p71/int1 72/int2/t0in 73/int3/t0in s0/t0 s1/t1 s2/t2 s3/t3 s4/t4 s5/t5 s6/t6 s7/t7 p07 p06 p05 p04 p03 p02 p01 p00 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 vp vddvpp s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8
LC86P6032 6/22 pin assignment package dimension (unit : mm) 3159 sanyo : qip-64e notes the qfp packages should be heat-soaked for 24 hours at 125 c immediately prior to mounting (this baking is called pre-baking). after pre-baking, a controlled environment must be maintained until soldering. the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. please solder within 8 hours. s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 s19 s18 s17 s16 vp vddvpp p17/pwm p16/buz p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p07 p06 p05 p04 p03 p02 p01 p00 s0/t0 s1/t1 s2/t2 s3/t3 s4/t4 s5/t5 s6/t6 s7/t7 s8/t8 s9/t9 s10/t10 s11/t11 s12/t12 s13/t13 s14/t14 s15/t15 test1 res xt1 xt2 vss cf1 cf2 vdd p80/an0 p81/an1 p82/an2 p83/an3 p70/int0 p71/int1 72/int2/t0in 73/int3/t0in 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LC86P6032 7/22 system block diagram interrupt control stand-by control clock generator cf rc x?tal ir pla prom control a15-a0 d7-d0 ta ce oe dasec vddvpp prom(32kb) pc acc b register c register alu psw rar ram stack pointer port 0 watch dog timer bus interface port 1 port 7 port 8 base timer sio0 sio1 timer 0 timer 1 adc int0 to 3 noise rejection filter real time service high voltage output xram (128 bytes) vfd controller
LC86P6032 8/22 pin description pin description table pin name i/o function description option function in prom mode vss - power supply pin (-) vdd - power supply pin (+) vp - power supply pin (-) for the vfd output pull-down resist vddvpp - power supply pin (+) *6 power for programming port0 p00 to p07 i/o 8-bit input / output port input for port 0 interrupt input/output in nibble units input for hold release pull-up resistor : present/not present output form : cmos/n-channel open drain port1 p10 to p17 i/o 8-bit input/output port data direction can be specified for each bit. other pin functions p10 : sio0 data output p11 : sio0 data input/bus input/output p12 : sio0 clock input/output p13 : sio1 : data output p14 : sio1 : data input/bus input/output p15 : sio1 clock input/output p16 : buzzer output p17 : timer 1 output (pwm output) output form : cmos/n-channel open drain data input/output d0 to d7 4-bit input port other pin functions p70 : int0 input/hold release/n-channel tr. output for watchdog timer p71 : int1 input/hold release p72 : int2 input/timer 0 event input p73 : int3 input with noise filter/timer 0 event input interrupt received format, vector address pull-up resistor : present/not present rising falling rising /falling h level l level vector port7 p70 p71 to p73 i/o i int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable 03h 0bh 13h 1bh input of prom control signal dasec (*1) oe (*2) ce (*3) port8 p80 to p83 i 4-bit input port other pin functions ad input port (4 port pins) s0/t0 to s6/t6 *7 o output for vfd display controller segment/timing in common s7/t7 to s15/t15 *8 o output for vfd display controller segment/timing in common internal pull-down resistor output s14/t14 : ta (*4) s15/t15 : a14 (*5) s16 to s23 *9 o output for vfd display controller segment internal pull-down resistor output address input a13 to a0 s24 to s29 *10 o output for vfd display controller segment res i reset pin
LC86P6032 9/22 pin name i/o function description option function in prom mode test1 o test pin should be left open xt1 i input pin for 32.768khz crystal oscillation when not used, connect to vdd xt2 o output pin for 32.768khz crystal oscillation when not used, should be left open cf1 i input pin for ceramic resonator oscillation cf2 o output pin for ceramic resonator oscillation all port options can be specified in bit units. *1 memory select input for data security *2 output enable input *3 chip enable input *4 ta ! prom control signal input *5 a14 ! address input *6 connect as shown in the following figure to reduce noise into vdd pin. short-circuit the vdd pin to the vddvpp pin. *7 s0/t0 to s6/t6 : not provided the pull-down resistor *8 s7/t7 to s15/t15 : provided the pull-down resistor (fixed) *9 s16 to s23 : provided the pull-down resistor (fixed) *10 s24 to s29 : not provided the pull-down resistor power supply vdd vss vddvpp lsi
LC86P6032 10/22 1. absolute maximum ratings at vss=0v and ta=25 c ratings parameter symbol pins conditions vdd[v] min. typ. max. unit supply voltage vddmax vdd,vddvpp -0.3 +7.0 input voltage vi(1) ports 71,72,3,8 res -0.3 vdd+0.3 vi(2) vp vdd-4.5 vdd+0.3 output voltage vo s0/t0 to s15/t15 s16 to s29 vdd-4. 5 vdd+0.3 input/output voltage vio ports 0, 1 port 70 -0.3 vdd+0.3 v ioph(1) ports 0, 1 cmos output at each pin -4 ioph(2) s0/t0 to s15/t15 at each pin -30 peak output current ioph(3) s16 to s29 at each pin -15 ioah(1) port 0 total of all pins -10 ioah(2) port 1 total of all pins -10 high level output current total output current ioah(3) s0/t0 to s15/t15 s16 to s29 total of all pins -130 iopl(1) ports 0, 1 at each pin 20 peak output current iopl(2) port 70 at each pin 15 ioal(1) port 0 total of all pins 40 low level output current total output current ioal(2) ports 1, 70 total of all pins 40 ma pdmax(1) dip64s ta=-30 to+70 c 760 mw power dissipation (max.) pdmax(2) qfp64e ta=-30 to+70 c 430 operating temperature range topr -30 +70 storage temperature range tstg -65 +150 c notes the qfp packages should be heat-soaked for 24 hours at 125 c immediately prior to mounting (this baking is called pre-baking). after pre-baking, a controlled environment must be maintained until soldering. the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. please solder within 8 hours.
LC86P6032 11/22 2. recommended operating range at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit operating supply voltage range vdd vdd 0.98 s tcyc 400 s 4.5 6.0 hold voltage vhd vdd ram and registers retain their pre-hold mode values 2.0 6.0 pull-down voltage vp vp 4.5 to 6.0 -35 vdd vih(1) port 0 (schmitt) output disable 4.5 to 6.0 0.4vdd +0.9 vdd vih(2) port 1 ports 72,73 (schmitt) output disable 4.5 to 6.0 0.75vdd vdd vih(3) port 70 port input/interrupt port 71 res (schmitt) output n-channel tr. off 4.5 to 6.0 0.75vdd vdd vih(4) port 70 watchdog timer output n-channel tr. off 4.5 to 6.0 0.9vdd vdd input high voltage vih(5) port 8 4.5 to 6.0 0.75vdd vdd vil(1) port 0 (schmitt) output disable 4.5 to 6.0 vss 0.2vdd vil(2) port 1 ports 72,73 (schmitt) output disable 4.5 to 6.0 vss 0.25vdd vil(3) port 70 port input/interrupt port 71 res (schmitt) n-channel tr. off 4.5 to 6.0 vss 0.25vdd vil(4) port 70 watchdog timer n-channel tr. off 4.5 to 6.0 vss 0.8vdd -1.0 input low voltage vil(5) port 8 4.5 to 6.0 vss 0.25vdd v operation cycle time tcyc 4.5 to 6.0 0.98 400 s continue
LC86P6032 12/22 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1,cf2 12mhz (ceramic resonator oscillation) refer to figure 1 4.5 to 6.0 11.76 12 12.24 mhz fmcf(2) cf1,cf2 3mhz (ceramic resonator oscillation) refer to figure 1 4.5 to 6.0 2.94 3 3.06 fmrc rc oscillation 4.5 to 6.0 0.4 0.8 2.0 oscillation frequency range (note 1) fsxtal xt1,xt2 32.768khz (crystal resonator oscillation) refer to figure 2 4.5 to 6.0 32.768 khz oscillation stable time period (note 1) tmscf(1) cf1,cf2 12mhz (ceramic resonator oscillation) refer to figure 3 4.5 to 6.0 0.02 0.2 ms tmscf(2) cf1,cf2 3mhz (ceramic resonator oscillation) refer to figure 3 4.5 to 6.0 0.1 1 tssxtal xt1,xt2 32.768khz (crystal resonator oscillation) refer to figure 3 4.5 to 6.0 1 1.5 s (note 1) the oscillation constants are shown on table 1 and table 2.
LC86P6032 13/22 3. electrical characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) port 1 port 0 without pull-up mos tr. output disabled pull-up mos tr. off vin=vdd (including off-state leak current of output tr.) 4.5 to 6.0 1 iih(2) port 7 without pull-up mos tr. port 8 vin=vdd 4.5 to 6.0 1 input high current iih(3) res vin=vdd 4.5 to 6.0 1 iil(1) port 1 port 0 without pull-up mos tr. output disabled pull-up mos tr. off vin=vss (including off-state leak current of output tr.) 4.5 to 6.0 -1 iil(2) port 7 without pull-up mos tr. port 8 vin=vss 4.5 to 6.0 -1 input low current iil(3) res vin=vss 4.5 to 6.0 -1 a voh(1) ioh=-1.0ma 4.5 to 6.0 vdd-1 voh(2) ports 0, 1 at cmos output ioh=-0.1ma 4.5 to 6.0 vdd-0.5 voh(3) s0/t0 to s15/t15 ioh=-20ma 4.5 to 6.0 vdd-1.8 voh(4) ioh=-1ma the current ioh at each pin should be between 0 and -1ma. 4.5 to 6.0 vdd-1 voh(5) s16 to s29 ioh=-5ma 4.5 to 6.0 vdd-1.8 output high voltage voh(6) ioh=-1ma the current ioh at each pin should be between 0 and -1ma. 4.5 to 6.0 vdd-1 vol(1) ports 0, 1 iol=10ma 4.5 to 6.0 1.5 vol(2) iol=1.6ma when the total current of the ports 0, 1 is not over 40ma. 4.5 to 6.0 0.4 output low voltage vol(3) port 70 iol=1ma 4.5 to 6.0 0.4 v pull-up mos tr. resistance rpu ports 0, 1 port 7 voh=0.9vdd 4.5 to 6.0 15 40 70 k ? continue
LC86P6032 14/22 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit ioff(1) output p-ch tr. off vout=vss 4.5 to 6.0 -1 a output off- leakage current ioff(2) s0/t0 to s6/t6, s24 to s29 without pull-down resistor output p-ch tr. off vout=vdd-40v 4.5 to 6.0 -30 pull-down resistor rpd s7/t7 to s15/t15, s16 to s23 with pull-down resistor output p-ch tr. off vout=3v vp=-30v 5.0 60 100 200 k ? hysteresis voltage vhis ports 0, 1 port 7 res output disable 4.5 to 6.0 0.1vdd v pin capacitance cp all pins f=1mhz unmeasured input pins are set to vss level ta=25 c 4.5 to 6.0 10 pf 4. serial input/output characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle t ckcy (1) 4.5 to 6.0 2 low-level pulse width t ckl (1) 4.5 to 6.0 1 input clock high-level pulse width t ckh (1) sck0, sck1 refer to figure 5. 4.5 to 6.0 1 cycle t ckcy (2) 4.5 to 6.0 2 low-level pulse width t ckl (2) 4.5 to 6.0 1/2 t ckcy serial clock output clock high-level pulse width t ckh (2) sck0, sck1 use pull-up resistor (1k ? ) when set to open- drain output. refer to figure 5. 4.5 to 6.0 1/2 t ckcy t cyc data set up time t ick 4.5 to 6.0 0.1 serial input data hold time t cki si0,si1 sb0,sb1 data set-up to sck0,1 data hold from sck0,1 refer to figure 5. 4.5 to 6.0 0.1 output delay time (serial clock is external clock) t cko(1) 4.5 to 6.0 7/12 t cyc +0.2 serial output output delay time (serial clock is internal clock) t cko(2) so0,so1 sb0,sb1 use pull-up resistor (1k ? ) when set to open- drain output. data hold from sck0,1 refer to figure 5. 4.5 to 6.0 1/3 t cyc +0.2 s
LC86P6032 15/22 5. pulse input conditions at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0 pulse countable 4.5 to 6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock selected to 1/1.) interrupt acceptable timer0 pulse countable 4.5 to 6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock selected to 1/64.) interrupt acceptable timer0 pulse countable 4.5 to 6.0 128 t cyc high/low level pulse width tpil(4) res reset acceptable 4.5 to 6.0 200 s 6. ad converter characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5 to 6.0 8 bit absolute precision et (note 2) 4.5 to 6.0 1.5 lsb ad conversion time = 16 tcyc (adcr2=0) (note 3) 15.68 (tcyc= 0.98 s) 65.28 (tcyc= 4.08 s) conversion time tcad ad conversion time = 32 tcyc (adcr2=1) (note 3) 4.5 to 6.0 31.36 (tcyc= 0.98 s) 130.56 (tcyc= 4.08 s) s analog input voltage range vain 4.5 to 6.0 vss vdd v iainh vain=vdd 4.5 to 6.0 1 analog port input current iainl an0 to an3 vain=vss 4.5 to 6.0 -1 a (note 2) quantizing error (1/2 lsb) is ignored. (note 3) the conversion time is the period from execution of the instruction to start conversion to the completion of shifting the a/d converted value to the register.
LC86P6032 16/22 7. current drain characteristics at ta=-30 c to +70 c, vss=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=12mhz for ceramic resonator oscillation fsxtal=32.768khz for crystal oscillator system clock : cf oscillator internal rc oscillator stopped 4.5 to 6.0 13 26 iddop(2) fmcf=3mhz for ceramic resonator oscillation fsxtal=32.768khz for crystal oscillator system clock : cf oscillator internal rc oscillator stopped 4.5 to 6.0 6.5 14 iddop(3) fmcf=0hz (when oscillator stops) fsxtal=32.768khz for crystal oscillator system clock : rc oscillator 4.5 to 6.0 4 10 ma current drain during basic operation (note 4) iddop(4) vdd fmcf=0hz (when oscillator stops) fsxtal=32.768khz for crystal oscillator system clock : crystal oscillator internal rc oscillator stopped 4.5 to 6.0 3.5 9 continue.
LC86P6032 17/22 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=12mhz for ceramic resonator oscillation fsxtal=32.768khz for crystal oscillator system clock : cf oscillator internal rc oscillator stopped 4.5 to 6.0 5 10 iddhalt(2) halt mode fmcf=3mhz for ceramic resonator oscillation fsxtal=32.768khz for crystal oscillator system clock : cf oscillator internal rc oscillator stopped 4.5 to 6.0 1.8 4.6 ma iddhalt(3) halt mode fmcf=0hz (when oscillator stops) fsxtal=32.768khz crystal oscillator system clock : rc oscillator 4.5 to 6.0 400 800 current drain at halt mode (note 4) iddhalt(4) vdd halt mode fmcf=0hz (when oscillator stops) fsxtal=32.768khz for crystal oscillator system clock : crystal oscillator internal rc oscillator stopped 4.5 to 6.0 20 60 iddhold(1) 4.5 to 6.0 0.05 30 current drain at hold mode (note 4) iddhold(2) vdd hold mode 2.5 to 4.5 0.02 20 a (note 4) the currents of output transistors and pull-up mos transistors are ignored.
LC86P6032 18/22 table 1. ceramic resonator oscillation circuit recommended constants (main-clock) oscillation type supplier oscillator c1 c2 murata csa12.0mtz 33pf 33pf csa12.0mt 33pf 33pf cst12.0mtw on chip 12mhz ceramic resonator oscillation kyocera kbr-12.0m 33pf 33pf murata csa3.00mg 33pf 33pf cst3.00mgw on chip 3mhz ceramic resonator oscillation kyocera kbr-3.0ms 47pf 47pf * for both c1 and c2, the k rank (10%) and sl characteristics must be used. table 2. crystal oscillation circuit recommended constants (sub-clock) oscillation type supplier oscillator c3 c4 daishinku dt-38(1ta252e00) 18pf 18pf 32.768khz crystal oscillation kyocera kf-38g-13p0200 18pf 18pf (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 ceramic resonator oscillation figure 2 crystal oscillation cf1 cf2 c2 c1 cf xt1 xt2 c4 c3 x?tal
LC86P6032 19/22 < reset time and oscillation stable time. > < hold release signal and oscillation stable time. > figure 3 oscillation stable time figure 4 reset circuit (note) the values of c res and r res should be determined such that reset time is at least 200 s, measured from the moment the power exceeds the vdd lower limit. power supply res internal rc resontor oscillation cf1, cf2 xt1, xt2 operation mode reset time tmscf tssxtal vdd vdd limit 0v reset unfixed instruction execution mode hold release signal internal rc resontor oscillation cf1, cf2 xt1, xt2 operation mode valid instruction execution mode hold tmscf tssxtal c res r res vdd res
LC86P6032 20/22 figure 5 serial input/output test conditions figure 6 pulse input timing conditions 0.5vdd vdd 1k ? 50pf tckcy tckl tckh tick tcki tcko sck0 sck1 si0 si1 so0, so1 sb0, sb1 tpil tpih
LC86P6032 21/22 notice for use the construction of the one-time programmable microcomputer with a blank built-in prom makes it impossible for sanyo to completely factory-test it before shipping. to probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. it is not possible to perform a writing test on the blank prom.. 100% yield, therefore, cannot be guaranteed. should be stored in dry conditions (qfp type only) the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. after opening the packing (qfp type only) the preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. after opening the packing, a controlled environment must be maintained until soldering. the environment must be held at a temperature of 30 c or less and a humidity level of 70% or less. please solder within 8 hours. a. shipping with a blank prom (data to be programmed by customer) this microcomputer is provided dip/qfp packages, but the condition before mounting is not same. refer to the mounting precedure as follows; recommended process of screening dip programming and verifying heat-soak 1505 c, 24 hr +1 -0 program reading test mounting recommended process of screening programming and verifying heat-soak 1505 c, 24 hr +1 -0 program reading test mounting baking before mounting 125 c, 24 hours baking qfp
LC86P6032 22/22 b. shipping with programmed prom (data programmed by sanyo) ps mounting qfp mounting baking before mounting 125 c, 24 hours baking dip

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